Sham Technology
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Sham Technology
by Maestro » Thu May 20, 2004 5:26 pm
What exactly is ULN2? and what is EB Enhanced Bandwidth? Are these new technologies endorsed by Intel, Samsung, Micron, Asus or any of the big boys? Are they even real? OR are they products of OCZ's overly creative PR drones? The only endorsements I can find on ULN2 and EB is from Wesley Fink on Anand, whose 13-page reviews look like they were written by the same OCZ marketeer who wrote the press releases.
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by infinitevalence » Thu May 20, 2004 6:49 pm
i dont know what ULN2 is but EB is an OCZ technology. its not a marketing gimic and its not endorced by anyone. its just a technology that OCZ devoloped to make its memory go a little faster than the other guys.
"Don't open that! It's an alien planet! Is there air? You don't know!"
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by drexor69 » Thu May 20, 2004 7:14 pm
LOL!!
This stuff is just like everything else OCZ does. That is to say they have some new marketing strategy every week to try to keep their brand in the news.
Anyone remember when they announced they were making their own IC's?
Even better yet, when they got busted lying about that they generated a "private email" that could be accessed on their web site talking about how they were doing it to make the IC's faster? If this was the case every IC house would have been doing it long ago and could have increased their yeilds significantly which would have resulted in BILLIONS of dollars of extra revenue generated.
How about the firmware that supposedly protected the IC from overvolting? Here's a newsflash, their supposed firmware was the voltage regulator the IC houses had to put down on the IC to drop the internal voltage to 1.8 volts.
And how about the recent heat sink grease that had no silver in it? Anyone know anyone that actually got theirs replaced? I personally know someone that has sent in 5 tubes separately and hasn't gotten anything back.
Like everything else they do it's total crap designed to hoodwink an unsuspecting public.
I used to think Anands was a credible site...
FYI for Mr Fink: The memory controller is all on the CPU of the Athlon 64 and it WILL NOT run more than 4 banks at PC3200.
idiots...
This stuff is just like everything else OCZ does. That is to say they have some new marketing strategy every week to try to keep their brand in the news.
Anyone remember when they announced they were making their own IC's?
Even better yet, when they got busted lying about that they generated a "private email" that could be accessed on their web site talking about how they were doing it to make the IC's faster? If this was the case every IC house would have been doing it long ago and could have increased their yeilds significantly which would have resulted in BILLIONS of dollars of extra revenue generated.
How about the firmware that supposedly protected the IC from overvolting? Here's a newsflash, their supposed firmware was the voltage regulator the IC houses had to put down on the IC to drop the internal voltage to 1.8 volts.
And how about the recent heat sink grease that had no silver in it? Anyone know anyone that actually got theirs replaced? I personally know someone that has sent in 5 tubes separately and hasn't gotten anything back.
Like everything else they do it's total crap designed to hoodwink an unsuspecting public.
I used to think Anands was a credible site...
FYI for Mr Fink: The memory controller is all on the CPU of the Athlon 64 and it WILL NOT run more than 4 banks at PC3200.
idiots...
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by Maestro » Thu May 20, 2004 7:15 pm
I think not! EB is a joke. OCZ's white paper sounds real technical--in fact it sounds almost too technical, like they packed in as much technical jargon as they possibly could into a 1 page document to confuse anyone with an engineering degree.
In any case, what they're talking about in their white paper is impossible because the whole memory controller circuit is INSIDE THE CHIPSET! You can't change how signals work without an Intel partnership to redesign their NorthBridge.
An average memory module has RAM chips, passives (capacitors and resistors) and an SPD chip on it, nothing more. Take a look at an EB module--there are no intelligent OCZ proprietary devices on it; there are no specially designed ASIC chips that alter the way signals are used. So where does this special EB technology reside? Inside the RAM chips that are made by Samsung and Hynix? Or inside the microscopic resistors? Software inside the SPD chip maybe?
In any case, what they're talking about in their white paper is impossible because the whole memory controller circuit is INSIDE THE CHIPSET! You can't change how signals work without an Intel partnership to redesign their NorthBridge.
An average memory module has RAM chips, passives (capacitors and resistors) and an SPD chip on it, nothing more. Take a look at an EB module--there are no intelligent OCZ proprietary devices on it; there are no specially designed ASIC chips that alter the way signals are used. So where does this special EB technology reside? Inside the RAM chips that are made by Samsung and Hynix? Or inside the microscopic resistors? Software inside the SPD chip maybe?
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by Apoptosis » Thu May 20, 2004 7:27 pm
I checked with OCZ about EB technology and they stated that is was a change in the SPD settings that the end user normally couldn't change. I've asked for some review samples, but OCZ hasn't gotten any EB modules out for me to look at yet so I'm not sure what values have been changed.
But in all honesty OCZ was open with me about EB technology in the fact that it's nothing more than SPD settings to improve performance on the IC's that they are using currently. (new revisions and IC's may not work with these more agressive timings)
But in all honesty OCZ was open with me about EB technology in the fact that it's nothing more than SPD settings to improve performance on the IC's that they are using currently. (new revisions and IC's may not work with these more agressive timings)
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by Maestro » Thu May 20, 2004 9:10 pm
yeah drex, i remember the big OCZ "lasering" scandal a few months ago that was propagated by Wesley Fink himself. It was a coverup for the exposee that they didn't really own a fab. That's when I first decided Fink was either a total idiot or on the take. Since that doofus story he's followed it up with two 13-page reviews on OCZ nonsense and no good reviews of Kingston or Corsair products. I conclude he's being bribed by OCZ, at least that's my opinion.
But back to Apo's statement that EB is just an SPD setting... Wrong again! OCZ doesn't mention anything at all about SPD in their EB white paper here: http://www.ocztechnology.com/displaypag ... Technology
And they don't mention changes to any of the parameters that are set in the SPD. Their EB white paper suggests that EB changes the way memory commands are executed. It's a big lie.
But back to Apo's statement that EB is just an SPD setting... Wrong again! OCZ doesn't mention anything at all about SPD in their EB white paper here: http://www.ocztechnology.com/displaypag ... Technology
And they don't mention changes to any of the parameters that are set in the SPD. Their EB white paper suggests that EB changes the way memory commands are executed. It's a big lie.
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by Maestro » Thu May 20, 2004 9:15 pm
from OCZ's white paper:
"a read command can be issued concurrent with an ongoing data burst. This means that the read command for the next data burst can be issued before an ongoing data transfer is exhausted with the result that the latency cycles are hidden behind the previous transfer"
WRONG!!!! commands are issued ONLY by the memory controller which is inside the northbridge (or inside CPU for AMD). No setting in the SPD, and nothing on the memory module itself, can change the time at which commands are issued. The memory module can only execute commands.
DDR2 does include a feature called Additive Latency which is similar to OCZ's description of EB, but since Additive Latency requires major changes to the architectures of the RAM chips and the memory controller I don't think that's what EB is.
"a read command can be issued concurrent with an ongoing data burst. This means that the read command for the next data burst can be issued before an ongoing data transfer is exhausted with the result that the latency cycles are hidden behind the previous transfer"
WRONG!!!! commands are issued ONLY by the memory controller which is inside the northbridge (or inside CPU for AMD). No setting in the SPD, and nothing on the memory module itself, can change the time at which commands are issued. The memory module can only execute commands.
DDR2 does include a feature called Additive Latency which is similar to OCZ's description of EB, but since Additive Latency requires major changes to the architectures of the RAM chips and the memory controller I don't think that's what EB is.
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