Intel & Micron's 25nm NAND

[Digital Puppy]

Intel and Micron plan to unveil new 25-nanometer flash memory chips via their IM Flash Technologies joint venture, the first commercial chip products made using advanced 25nm manufacturing technology. An announcement is expected on Monday, but here is some in-depth information regarding the process and their partnership with Micron:

Said to be First-Ever Use of 25nm Process

In an effort to remain a full process node ahead of other NAND flash manufacturers, Intel and Micron today announced that the companies' IMFT joint venture has now introduced a 25nm 64Gb MLC NAND chip. This translates to 8 gigabytes on a single chip. With a die size of 167mm² the device can fit into a standard TSOP package.

The announcement follows the companies' May 2008 introduction of a 34nm 32Gb NAND.

At a die size of 167mm² a 300mm fab should be able to manufacture just over 400 dice per wafer. This gives a manufacturing cost of about $4.00 per chip, or $0.50/GB. Compare this to a more common 45nm MLC NAND on a 300mm line which should cost about $1.75/GB. Since the price of NAND flash has been hovering around $2.00/GB for the past year, and seems poised to continue at that price through 2010, the 25nm process will give the companies a significant margin boost over their current 34nm chip whose cost we estimate at $1.00/GB.

The companies made it very clear that they do not plan to drive prices down to follow cost. Instead, we can expect for Micron and Intel to continue to charge market prices and simply pocket larger margins than can their competition.

Both companies are currently sampling to select customers and controller makers. Both also remarked that this was one further step that would help bring SSDs into the mainstream.

The companies point out that they entered the market with a 72nm technology in 2006, which they believe was about 2 years behind their competition, but caught up and surpassed these competitors by as much as a year with the 34nm part, and are maintaining this leadership by migrating to 25nm at the same time that some of their competitors are ramping their 30nm-generation processes.

Not only will this new process allow Micron and Intel to profit more than their competition, but it also allows them to squeeze more gigabyte production out of their Lehi and Manassas lines before having to equip their new fab in Singapore.

Those who want to have a better understanding of the derivation of the numbers above and how the NAND market behaves should look into the Objective Analysis report: Understanding the NAND Market, which can be found at http://www.Objective-Analysis.com/Reports.html#NAND.

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