SATA 6 Gbps: The Right and the Wrong Way
Posted: Tue Nov 03, 2009 10:34 pm
With the recent and upcoming release of drives utilizing the latest SATA 6 Gbps interface, manufacturers are rushing out motherboards to support the new standard. Since the P55 chipset, or any other for that matter, only support up to SATA 3 Gbps so companies have to resort to a third party controller. The only one being used, that I know of at least, is the Marvell SE9123. Using a single PCI-Express 2.0 lane (500 MB/s in both directions), it supplies two ports, but no RAID.
You probably noticed the potential bottleneck here, third generation SATA can provide bandwidth up to 600 MB/s, while the PCI-E lane will only do 500 MB/s. Well, that’s hardly a problem considering even the fastest SSDs aren’t reaching those speeds, for now at least. Anyway, I’m heading off course.
For some reason, Intel only gifted the P55 chipset with PCI-Express 1.0 lanes (250 MB/s in both directions) and there lies the issue. For a SATA 3 Gbps controller, it’s not too bad, but for a next generation controller, it causes a major bottleneck. There are two ways around this; one of them being quite obviously the better solution.
The easy, scratch that, wrong way is to take PCI-E 2.0 lanes off the processor and feed them directly to a SATA 6 Gbps (and USB 3.0) controller. However, there is a major downside. Remember that Lynnfield only has 16 lanes and you need 8 of them for a graphics card. Once these two controllers are enabled, you’re left with 14 lanes and the hardware is only designed to give 8 of them to the graphics card so you’re essentially wasting the remaining ones. The ugly part is that you lose CrossFire and/or SLI since the second slot can’t live off 6 lanes.
Then there’s the other way - the right way. It involves a PLX chip, similar to what ATI uses on dual-GPU cards. Its job is relatively simple, take 4 PCI-E 1.0 lanes and turn them into a pair of PCI-E 2.0 lanes. Simple enough. It’s just as fast as the other implementation, bare a few nanoseconds of latency, while retaining CrossFire and/or SLI capabilities. With the remaining 4 PCI-E 1.0 lanes, you can still have two PCI-E 1x slots, a PATA/SATA 3 Gbps controller and whatever else you can think of.
I’m not naming anyone, but you should be able to figure it out fairly easily ;)
You probably noticed the potential bottleneck here, third generation SATA can provide bandwidth up to 600 MB/s, while the PCI-E lane will only do 500 MB/s. Well, that’s hardly a problem considering even the fastest SSDs aren’t reaching those speeds, for now at least. Anyway, I’m heading off course.
For some reason, Intel only gifted the P55 chipset with PCI-Express 1.0 lanes (250 MB/s in both directions) and there lies the issue. For a SATA 3 Gbps controller, it’s not too bad, but for a next generation controller, it causes a major bottleneck. There are two ways around this; one of them being quite obviously the better solution.
The easy, scratch that, wrong way is to take PCI-E 2.0 lanes off the processor and feed them directly to a SATA 6 Gbps (and USB 3.0) controller. However, there is a major downside. Remember that Lynnfield only has 16 lanes and you need 8 of them for a graphics card. Once these two controllers are enabled, you’re left with 14 lanes and the hardware is only designed to give 8 of them to the graphics card so you’re essentially wasting the remaining ones. The ugly part is that you lose CrossFire and/or SLI since the second slot can’t live off 6 lanes.
Then there’s the other way - the right way. It involves a PLX chip, similar to what ATI uses on dual-GPU cards. Its job is relatively simple, take 4 PCI-E 1.0 lanes and turn them into a pair of PCI-E 2.0 lanes. Simple enough. It’s just as fast as the other implementation, bare a few nanoseconds of latency, while retaining CrossFire and/or SLI capabilities. With the remaining 4 PCI-E 1.0 lanes, you can still have two PCI-E 1x slots, a PATA/SATA 3 Gbps controller and whatever else you can think of.
I’m not naming anyone, but you should be able to figure it out fairly easily ;)
