NVM Express Specification Released for PCIe-based SSDs
Posted: Tue Mar 01, 2011 7:40 pm
NVM Express Specification Released for PCIe-based SSDs
The NVMHCI Work Group has released the NVM Express 1.0 specification that will allow the industry to create PCI Express® (PCIe®)-based Solid-State Drives (SSDs) that will improve the performance of SSDs operating on multi-core architectures, as well as improve time to market. Intel, along with 70 NVMHCI members, collaborated on the spec so OEMs can create devices that work with multiple vendors.
The NVMHCI Work Group has released the NVM Express 1.0 specification that will allow the industry to create PCI Express® (PCIe®)-based Solid-State Drives (SSDs) that will improve the performance of SSDs operating on multi-core architectures, as well as improve time to market. Intel, along with 70 NVMHCI members, collaborated on the spec so OEMs can create devices that work with multiple vendors.
NVM Express – The Optimized PCI Express* SSD Interface
NVM Express defines an optimized register interface, command set, and feature set for high performance PCI Express* based Solid-State Drives (SSDs). This specification is intended for hardware component designers, system builders and device driver (software) developers.
The significant advances in performance enabled by non-volatile memory based storage technology, as embodied in PCI Express SSDs, has demanded the surrounding platform infrastructure evolve to keep pace and allow the system to realize the full potential these devices have to offer. The ongoing rapid development and improvement in this technology is expected to continue into the future and so the platform infrastructure must be positioned to keep pace with expected PCI Express SSD evolution. This was a primary goal in the development of the NVM Express interface. The NVM Express interface is architected and designed to allow the full performance potential of these devices to be unlocked now and into the future.
The interface includes several key features for scalability. A device may support up to 64K I/O queues with up to 64K commands per queue. The interrupt architecture supports MSI-X and interrupt aggregation. The interface efficiently supports multi-core by ensuring thread(s) may run on each core with its own queue & interrupt without any locks required. For Enterprise class solutions, there is support for end-to-end data protection, security & encryption capabilities, as well as robust error reporting and management capabilities.
There are numerous benefits to a standard interface through the interoperability it fosters. Each OS vendor may confidently write a driver that works for devices from multiple vendors. OEMs may procure devices from diverse suppliers that all implement a consistent feature set. Time to market is reduced as validation times shrink with standard drivers and OEMs may leverage the same test suites across devices.
For an overview of NVM Express, including the motivations for developing the interface, refer to the whitepaper "NVM Express Explained".
NVM Express was developed by the more than 70 members of the Non-Volatile Memory Host Controller Interface (NVMHCI) Workgroup. This specification was previously referred to as Enterprise NVMHCI. However, the interface is scalable and may apply to Enterprise and Client application.
Implementation of the NVM Express (i.e., Non-Volatile Memory Host Controller Interface Specification) requires a license from Intel. Contributors/Adopters of the NVMHCI Workgroup have signed the Non-Volatile Memory Host Controller Interface Specification Contributor/Adopter Agreement in order to be licensed to use and implement this Specification. This Contributor/Adopter Agreement provides Contributors/Adopters with a reciprocal, royalty-free license to certain intellectual property rights from Intel and other Contributors for their products that are compliant with the licensed versions of the Non-Volatile Memory Host Controller Interface Specification.