who can define Mulitple Clock Domain (MCD)
Posted: Fri Oct 24, 2008 10:20 pm
I heard many cases mentioning MCD. Who can give me a clear and accurate definition about it? Thanks.
you mean like on Phenom processors where different areas are driven by different clock signals and you can customize some values?
AMD's Phenom has 5 clock domains, one for each core and then there is the one for the L3 cache.