AMD Discusses Fusion Processors at ISSCC
Posted: Tue Feb 09, 2010 9:19 am
Yesterday afternoon at ISSCC in San Francisco, AMD presented details on the forthcoming 32nm Fusion APU slated for 2011, codenamed “Llano.” AMD Senior Fellow, Samuel Naffziger, walked attendees through several power management innovations to the x86 core, which he has also detailed in this blog post: http://links.amd.com/ISSCC This update to Fusion further validates AMD’s strategy to provide processing performance that addresses modern workloads such as HD video, immersive graphics, gaming and multimedia. AMD will be disclosing more details on Fusion closer to the launch.
Welcome to our first blog solely dedicated to regular contibutions on Fusion. Here we plan to both define the larger Fusion strategy as it pertains to AMD’s overall engagement in the industry, as well provide regular updates on the hardware and software innovations that result. Today we’re talking hardware, specifically x86 power management enhancements on the first product in AMD’s Fusion family of processors.
At AMD, we live by the mantra that the Future is Fusion and our global engineering teams are working aggressively to deliver the industry’s first accelerated processing unit (APU) in support of it. That said, the consumer trends that led AMD to embark toward developing APUs began years ago; the idea wasn’t born in either a CPU or a GPU, but was born in how consumers began using their PCs. Things like: streaming video, immersive gaming, 3D user interfaces, enhanced multimedia and other compute intensive tasks became the norm rather than the exception. As an engineer, my job is to help figure out how the nuts and bolts can best fit together to help improve the user’s experience; our team is presenting today at the International Solid State Circuits Conference (ISSCC) in San Francisco some of the results of those efforts.
Let me first take a step back and recap how the first AMD APU, codenamed “Llano,” is expected to look when it enters the market:
* Four CPU cores, DDR3 memory and a DirectX® 11 capable SIMD engine integrated on-die.
* “Llano” is scheduled to be the first design from AMD using 32nm SOI process technology
* AMD plans to launch “Llano” in 2011
* This APU is expected to first appear within the forthcoming “Sabine” platform for mainstream notebooks
The AMD paper at ISSCC is specifically about some important power management enhancements made to the x86 cores on “Llano” to increase performance per-watt and help make the CPU/GPU combination even more compelling. Without diving too deep into the technical details, these innovations include:
* Core power gating – a feature of the processor that disconnects power to the core when it’s not in use, helping to reduce overall power consumption and extend battery life. AMD’s SOI process allows us to use more efficient NFET transistors for power gating as opposed to the PFET transistors used with a bulk silicon manufacturing process. In addition, AMD uses the actual chip package to re-distribute the gated ground rather than an additional thick metal layer used by other gating schemes. In total, this equates to a greater than 90% estimated reduction in leakage power.
* Digital APM Module – Measuring core power consumption is extremely important for a processor to understand how hot it’s running and when performance can be increased within a thermal constraint. There are two schools of thought here: measure temperature and amps via analog methods, or measure power consumption digitally. The former is subject to a variety of environmental issues (temperature in the room, dust on the fan, etc.), while the latter is more accurate and repeatable. AMD has implemented a digital power management technique that allows us to measure power consumption more accurately, thus helping to optimize performance-per-watt in real-time.
* De-Populated Clock Grid – Clock gating is a technique where the clock signal is combined with a control signal to either enable or disable the clock for certain parts of the circuit. This helps save power by effectively shutting down portions of a digital circuit when they are not in use and is used extensively in AMD’s x86 core. An effective way to get this clock signal to every part of a chip that needs it, with the lowest skew, is a metal grid. In a large microprocessor, the power used to drive the clock signal can be over 30% of the total power used by the entire chip. We’ve been able to dramatically reduce the amount of metal and buffering in this system to reduce clock switching power by an estimated factor of 2.
And just to show how real it all is, the picture below shows the core’s more than 35 million transistors that fit within 9.69mm2 (not counting the 1MB of L2 cache shown on the right):
I’m very pleased we are highlighting these x86 innovations from AMD and the underlying technologies that are designed to make AMD’s Fusion processors shine as “Llano” gets closer every day.
What are your thoughts on Fusion?
Samuel Naffziger, Senior Fellow, AMD
Samuel Naffziger is a senior fellow at AMD. His postings are his own opinions and may not represent AMD’s positions, strategies or opinions. Links to third party sites are provided for convenience and unless explicitly stated, AMD is not responsible for the contents of such linked sites and no endorsement is implied.