Difference between SpeedStep and EIST

[heidrickla]

SpeedStep is operating system controlled, while EIST is completely hardware controlled. Previous generations of Intel processors implemented the Intel basic SpeedStep technology. It switches both voltage and frequency between two distinct states: Lowest Frequency Mode (LFM) and Highest Frequency Mode (HFM) by using the platform C3-idle state. While achieving low-power operation during LFM, the basic SpeedStep architecture does not fully address demand-based switching needs. The long system unavailability time during transitions limits the switching frequency due to interaction with streaming devices such as Audio Codec ’97 (AC ’97) and the Universal Serial Bus (USB). Additionally, having only two fixed operating points limits operating point optimization according to the load. EIST is a multi-point Enhanced Intel SpeedStep technology optimized for demand-based switching.

The Enhanced Intel SpeedStep technology attempts to address the following challenges:

Minimizing system and processor unavailability. Operating point switching requires voltage to be transitioned over a wide range (e.g., from 0.9V to 1.5V). Physical limitations of the power delivery system translate this demand to over 100µs delay. A full clock generator Phase-Locked-Loop relock requires approximately 30µs. The architecture needs to ensure system memory access unavailability will not exceed 10-15µs, to match isochronous device needs.
Self-managed voltage and frequency stepping. The Enhanced Intel SpeedStep technology requires the migration of the mechanism from the chipset into the processor. This introduces two challenges: (a) how to sequence the operation when the processor clock is halted and (b) how to prevent loss of system events, such as interrupts and snoops, previously blocked by the chipset during the transition.
The Enhanced Intel SpeedStep technology uses three novel principals to address the challenges stated above:

Voltage-Frequency switching separation. Unlike previous architectures, the Enhanced Intel SpeedStep technology separates the voltage and frequency transition stages.

Voltage is stepped in short increments, preventing clock noise and allowing processor execution during the voltage transition stage. Thus, system memory and the processor are made available during the longest segment of the operating point transition, thereby minimizing unavailability time to only the frequency transition stage.
Clock partitioning and recovery. During the Enhanced Intel SpeedStep technology transition, only the core clock and Phase-Locked-Loop are stopped, while the bus-clock is kept running. The Enhanced Intel SpeedStep technology logic was partitioned such that only the command interface and core controls operate on the core clock, while the sequencer and interrupt interface operate on the bus clock. Thus the logic can be kept active constantly, even though the core clock has been halted.

Additionally, the clock circuitry was designed to utilize the active bus-clock to shorten core-clock relock time considerably. Thus core-clock restart time is set to only 10µs, minimizing the processor inactive time.
Event blocking. Interrupts, pin events, and snoop requests sent during the frequency transition stage must not be lost, even though the core clock is not available to serve them.

The Enhanced Intel SpeedStep technology logic samples all pin events when the core clock is stopped. These are re-sent to the processor once the core clock is available, preventing loss of events.

Bus events (such as snoops and interrupt messages) are blocked off using the native BNR# protocol, which captures the bus for the frequency transition period. Thus bus and pin events are not missed; they are serviced once the core is capable and running.
Consequently, the Enhanced Intel SpeedStep technology provides a flexible, multi-point operating mode, completely self managed, and with a very low CPU and memory unavailability time, which optimizes its power and performance according to demand. I hope this sheds some misconceptions about EIST, and highlights the true advantages it has over SpeedStep.